1. Field of the Invention
The invention relates generally to a frequency modulating circuit, and more particularly to a device and method for automatically modulating a phase locked loop.
2. Description of the Related Art
A phase locked loop (PLL) is a circuit able to synchronize an output signal generated by an oscillator with a reference or input signal in frequency and phase.
A voltage-controlled oscillator in a phase locked loop used to let voltage as the frequency control variable. In addition to voltage, current or another electronic variable parameter may be applied. Generally, when the output frequency of a voltage-controlled oscillator (VCO) is out of a predetermined range, then the phase locked loop may not lock the desired frequency. The predetermined range corresponds to an oscillation frequency in relation to a control voltage characteristic of the voltage-controlled oscillator. If an oscillation frequency of the voltage-controlled oscillator is over a stated maximum value of the predetermined range, or below the minimum value of the predetermined range, it may result in a problem where the output signal frequency of the phase locked loop is incapable of corresponding to an input signal of the phase locked loop. During this condition, the phase locked loop becomes unable to lock. Though the output signal of the phase locked loop may oscillate to drive the loop back to “locked”, the oscillations are still so high or low in frequency, they are unable to prevent the phase locked loop from not performing its intended functions. Therefore, it is desirable to provide a device and method that is capable of “locking” the phase locked loop when the loop is unable to achieve frequency locking.
One process to achieve improved performance is disclosed in U.S. Pat. No. 6,956,416. The patent application discloses the reduction of the chances that the phase locked loop produces unintended operating states. A control circuit periodically determines whether the phase lock is properly operating according to an output signal of the phase locked loop and a control voltage of the voltage-controlled oscillator. When the phase locked loop reaches a locked condition, the control circuit asserts a STABLE signal to indicate the output signal may be used. Otherwise, if the phase locked loop cannot reach the locked condition, the control circuit subsequently reset the phase locked loop according to an ENABLE signal. After being reset, the phase locked loop may restart and then reach the locked state. From the above-mentioned, however, no clamping method for recovering the phase locked loop from an incapable of lock state, back to a capable of lock state is presented.
Consequently, there is a need for a more reliable and improved phase locked loop device with reduced cost. Further, it would be desirable to provide a phase locked loop device and control method that is capable of detecting and ensuring that the phase locked loop is maintained.